A prequel to FPGA and ASIC design using small-scale integration chips

A prequel to FPGA and ASIC design using small-scale integration chips
A comprehensive set of exercises
Yuri Panchul, 2026-07-23

Ideal for school students, but also useful for university students, so that they do not try to “program” in Verilog, but instead use Verilog code to build hardware structures.

Can be used to develop problem-solving skills and focus for the children in a summer camp setting, somewhere in a Sierra-Nevada forest, without access to the internet or AI (an “AI Detox Camp”). No computers or smartphones, only paper IC datasheets, breadboards, 9-volt batteries, color pencils and sheets of paper.

I also recommend using 5V-tolerant LEDs, buttons with embedded pull-down resistors, a stable 5V breadboard power supply and already assembled 555-based clock generators. This eliminates a lot of tediousness with inserting hundreds of resistors and other nonsense customary in 7400 and CMOS 4000 kits since the 1970s. I also removed all the transistors, SR-latches, JK-flip-flops, etc because a modern RTL (Register Transfer Level) designer never sees this stuff in the workplace.

Basics

1. Demo 4081 (AND), 4071 (OR), 4069 (NOT), 4070 (XOR).
2. Demo 4013, D-flip-flop (DFF) with asynchronous reset.
3. Demo 4029 counter.
4. Demo 4015, a serial-to-parallel (SiPo – serial input / parallel output) shift register.
5. Explore a common-cathode single-digit seven-segment display and drive it with the 4511 chip.
6. Demo 4008, a 4-bit combinational adder. Use three 4511 chips to display the arguments and the result on three seven-segment displays.

Building blocks

1. Demo 4048, a reconfigurable gate.
2. Demo 4014, a parallel-to-serial (PiSo – parallel input / serial output) shift register.
3. Demo 4063, a 4-bit combinational comparator.
4. Demo multiplexers (MUXes) using 4051, 4052, 4053, 4019.
5. Demo 4028, BCD-to-decimal decoder. It will be used in projects to substitute a MUX with a combination decoder+selector based on AND and OR gates.
6. Demo 4532, 8-to-3 priority encoder. Use 4511 to display the output in decimal form.
7. Demo 4017, decade counter with decoded outputs.
8. Demo 40105, a FIFO.
9. Demo 40108, a 4×4 register file.
10. Demo 40181, a 4-bit ALU.

Mini-projects for review

1. Full adder using basic gates.
2. 2-bit combinational adder using full adder and half adder.
3. Replace 4051 mux with an equivalent design using 4028 decoder and a selector based on AND and OR gates.
4. Replace 4051 mux with an equivalent design using 4028 decoder and a selector based on 4086 AND-OR-NOT and 4069 inverter.
5. Replace 4052 mux with an equivalent design using 4555 decoder and a selector based on AND and OR gates.
6. Replace 4052 mux with an equivalent design using 4555 decoder and a selector based on 4086 AND-OR-NOT and 4069 inverter.
7. Demo 4019 data selector performing a bit-mask merge of two bit vectors. Compare it with an equivalent implementation using basic gates.
8. Johnson counter using 4015 shift register and 4069 inverter.

Projects

1. Demo 4032, a bit-serial adder. Combine it with two parallel-to-serial 4014 shift registers, one serial-to-parallel 4015 shift register and three 4511 display drivers to show the arguments and the result. Compare this way of doing addition to addition using a combinational adder 4008.
2. Replace 4032 with an equivalent design using logic gates (AND/NAND/OR/NOR/NOT/XOR) and a D-flip-flop (DFF) for carry.
3. Combine three 40105 FIFOs with a 4008 adder to add numbers coming in different clock cycles and control the flow of the result with backpressure.
4. Finite state machines (FSMs) for bit sequence recognition. Implement using basic gates and DFFs. You can use 4076 and 40174 DFFs instead of 4013.
5. Build a bit-serial comparator in FSM fashion using basic gates and D-flip-flops. Compare with a combinational comparator built using 4063.