On June 7, 2026, at the Verilog Meetup at Hacker Dojo, we created small-scale integration (SSI) demos using C4000-series chips. They are a stepping stone to hardware description language (HDLs), making basic gates, flip-flops, and multiplexers easier to understand because every signal is physically visible. Learning these basic elements lays the foundation for becoming a CPU designer.
To demonstrate the benefits of using simple 74LS-series SSI devices, I designed and built a fully functional 8-bit CISC CPU with 64 kB of addressable memory. The CPU is capable of running games and interfacing with peripherals such as LCD character display, LED matrix, keyboard, keypad, and VGA monitor. In general, SSI chips are outdated for modern tasks since they are less cost- and power-efficient than microcontrollers, ASICs and FPGAs for most applications. However, their simplicity and intuitive nature made them an excellent choice for this self-education project. Since SSI chips directly implement basic digital logic components such as gates and registers, designing with them is straightforward.
The CPU is an accumulator-based design*, with the A register at the center of many operations. In addition, it includes ALU flags, an index register, a stack pointer, an instruction register, a 3-bit step counter, a 16-bit program counter, a 16-bit memory address register (MAR), and a temporary register.
*Accumulator-based CPUs were popular in computers of the 1950s, as well as in early personal computers of the 1970s, such as the Apple II, which used the MOS Technology 6502 CPU. During that era, memory access was faster relative to other CPU operations, such as arithmetic addition, so having many programmer-visible registers or caches was not a priority, especially in smaller systems.
The CPU is horizontally microcoded** with 48 control signals.
**This design technique was very popular during the 1960s and 1970s in IBM mainframes and DEC minicomputers. It allowed computer architectures to evolve without redesigning the datapath, enabling product lines with varying cost and performance. Later, the use of horizontal microcode declined because it is not well suited to pipelined processors, although it is still used in some situations.
Returning to the meetup demos, we built two boards at the Verilog Meetup: one soldered and one breadboard-based, each highlighting a single digital logic element. One board demonstrates an AND gate, while the other demonstrates an OR gate. The buttons provide physical inputs to the gates, and the LEDs provide physical outputs, making it much easier to observe the circuits in operation.
These demo boards abstract away many of the details that might otherwise confuse beginners. For example, the power supply is already regulated and plugs directly into the breadboard. The LEDs do not require current-limiting resistors, eliminating another component. The buttons are mounted on dedicated PCBs with built-in pull-down resistors, making them easier for beginners to use.
Having worked with these chips, I am now learning SystemVerilog, a hardware description language, as a logical next step.
As mentioned earlier, SSI is an excellent introduction to HDLs because it develops the habit of thinking in terms of generated schematics. A standard way to introduce students to HDLs is through FPGA-based laboratory exercises.
However, this is not the only possible next step. Another idea is to combine SSI chips with open-source ASIC design tools such as Yosys. An ASIC (Application-Specific Integrated Circuit) is a custom chip manufactured in a silicon foundry for a specific application. We plan to experiment with a Yosys-based toolchain by modifying it to generate SSI-based schematics from SystemVerilog code.
Will keep you posted.