Getting Started with Verilog, FPGA, ASIC Design and Verification

Learning digital design is similar to learning to play a flute or going to the gym to put yourself in physical shape. The basics are simple, but you need to exercise in order to do something impressive, like playing in a concert or winning a sports competition. If you just watch the PowerPoint slides on how to press keys on a flute, or watch YouTube videos on how to use a rowing machine in a gym, or even ask AI on how to make vibrato – you are not going to make any progress whatsoever.

So exercises should be incorporated into the learning from day one. Most university students do not do enough exercises which leads to their poor performance in job interviews. Instead:

• First, students should use simple exercises in a Verilog simulator and on an FPGA board to learn basic Verilog syntax and flow.
• Second, they need to clearly understand the sequential logic, organizing calculations into clock cycles, and static timing, solving delay problems within a clock cycle.
• Third, they need to understand microarchitectural concepts, such as pipelines (and not only a CPU pipeline), and microarchitectural building blocks, such as FIFOs and arbiters, when and how to use them.

In parallel with RTL (Register Transfer Level), students should learn the basics of verification, and not in a primitive form, like ad hoc testbenches with pound delay and checking signal value after it, but in a form of checking microarchitecturally interesting RTL design against a transactional model that has no clocks, but queues and scoreboards. Without learning a little bit of modern DV (Design Verification), event a student who specializes in RTL would not be able to find many corner cases of his non-trivial RTL design exercise solutions.

For the starters:

When you are just starting, I recommend reading the presentation used for orientation at Verilog Meetups. Then you need to do three activities in parallel:

1. Read Chapter 4 of the textbook David Harris and Sarah Harris, Digital Design and Computer Architecture, RISC-V Edition. You can also use the instructor resources, particularly slides, to digest the information faster.
2. You can also use the instructor resources for the Harris & Harris textbook, particularly the slides, to digest the information faster.
3. Do the homework using Icarus Verilog from systemverilog-homework repository.
4. Get an FPGA board, run and review all the examples in basics-graphics-music repository.

Do not use AI to do the homework. If you use AI for the exercises you will learn nothing. You may as well go to a bar and drink a beer – the result will be the same. You are learning by overcoming difficulties, your brain will remember how you struggled with blocking and non-blocking assignments trying to put clock cycles right, and you will automatically solve or avoid such situations for the rest of your career. With AI there would be no such memory, you will not register the information and forget it right away. And by the way, AI will not help you with more advanced microarchitectural exercises, starting from part 6 of SystemVerilog Homework.
 

 

If you decided to continue:

Add the following books to your reading routine:

1. Logic Design and Verification Using SystemVerilog – March 1, 2016 by Donald Thomas. Not to be confused with the old (starting 1980s) books of the same author.
2. Digital Design: A Systems Approach by William James Dally and R. Curtis Harting.
3. Verilog Gotcha articles by Stuart Sutherland, Don Mills and Chris Spear: Part 1 and Part 2.
4. Articles by Cliff Cummings.

Do not substitute reading books with chatting with AI. When you read a book, you get the map of the area from the brain of the expert author. When you chat with AI, you get an averaged wisdom of a lot of dilettantes, who 1) make mistakes and 2) have a wrong focus.

For example, AI directed one of the learners toward a construct always_latch which should not be used to instruct beginners. It is used to model D-latches, a primitive relevant to clock gating for dynamic power savings or to advanced topics (timing borrowing, latch arrays). There is no point in exposing a student to low-power techniques before he is trained in building sequential logic using D-flip-flops, a state element in 99% of design situations. A student who read about D-latch-based design but cannot build a pipeline or a FIFO using D-flip-flops is useless for design work in an electronics company.

Likewise, you should consult IEEE 1800-2023 Standard for SystemVerilog when you need to clarify anything about the language specifics:

Asking an LLM about details of the SystemVerilog language is notoriously unreliable, as you can see in the screenshots below. Sure, it will tell you “you are absolutely right” when you catch it on false information, but that is true only if you already know the answer. In addition, when you consult the standard document, you understand the broader context and the logic of the language.
 

 
If you cannot pass part 2 of the SystemVerilog Homework (sequential basics), the probability of you passing an interview for an internship or a job in a typical electronics company is low. On the other hand, if you can pass all parts of the Homework, and you also have a basic clue about static timing analysis, then the probability is high, particularly for a junior position. For a senior position you also need to master clock domain crossing (CDC), low power techniques and more computer architecture.

We would recommend to add the following two Challenges on the top of your SystemVerilog Homework exercise routine. Please do them without AI, AI engines already know how to do them (back in the summer of 2025 they did not), so solving them with AI will not teach you much:

• SystemVerilog Microarchitecture Challenge for AI No.1.
• SystemVerilog Microarchitecture Challenge for AI No.2. Adding the Flow Control.

Finally, in order to get exposed to ASIC static timing analysis (STA) we would recommend to routinely convert your designs from FPGA-based to ASIC-based using the techniques we described in the following two articles, which also contain lectures on STA and other aspects of ASIC design:

• Moving your design from FPGA to ASIC using Verilog Meetup variant of the Tiny Tapeout
• A push for better workforce development in EE starts with the Verilog Meetup at Cal Poly San Luis Obispo

 

 

If you want to specialize in design verification:

Design Verification (DV) is a separate profession but the required skillset has a significant overlap with that of an RTL Design engineer. Both types of engineers need to understand what happens each clock cycle (sequential logic) and the work of microarchitectural objects, such as pipelines, FIFOs, multi-bank memories, arbiters, etc. This is necessary because they usually debug the design together.

However, a DV engineer typically does not need to know what happens within a cycle: propagation delays, setup and hold times, negative slack etc. This is between an RTL engineer and a Physical Design (PD) engineer. On another side, an RTL engineer does not typically need to know about the work of a transaction-level golden reference mode used to check his RTL.

A fundamental issue with many DV tutorials: they focus on language (SystemVerilog) and library (UVM) and use trivial examples: ALU, single transaction at a time APB BFM (Bus Functional Model) etc. In order to capture the spirit of the DV profession more accurately, even beginner tutorials should use pipelined blocks and out-of-order protocols to demonstrate the scoreboarding techniques.

You can see some techniques, such as using SystemVerilog queues to build self-checking testbenches, in some examples within already mentioned SystemVerilog-Homework and Basics-Graphics-Music GitHub repositories. See for example:

1. labs/4_microarchitecture/4_2_fifo/4_2_9_a_plus_b_using_wrapped_fifos
2. labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter
3. non-uvm-axi-lite-verification-ip/08_axi_master_slave_monitor/50_axi_pipelined_wr_out_of_order_rd

Here are some books on Design Verification we recommend to read in parallel with analyzing the exercises:

1. SystemVerilog for Verification: A Guide to Learning the Testbench Language Features 3rd ed. 2012 Edition by Chris Spear and Greg Tumbush.
2. Writing Testbenches using SystemVerilog 2006th Edition by Janick Bergeron.
3. Getting Started with UVM: A Beginner’s Guide

 

 

If you want to specialize in CPUs:

A good place to start is to read the elementary introduction to CPU architecture (instruction set) and microarchitecture (pipeline structure) in Chapters 6 and 7 of the already mentioned textbook David Harris and Sarah Harris, Digital Design and Computer Architecture, RISC-V Edition.

There are several simple CPU cores in the Basics-Graphics-Music GitHub repository that can be used for simulation and synthesis. The simplest one, schoolRISCV, is described in the second half of the article “Bootstrapping Azerbaijan as a new center of ASIC design + Verilog Meetup #6 in Silicon Valley”.

However if you want to see a core that is closer to industrial CPUs running Linux, you can pre-order the next book By Harrises, RISC-V System-on-Chip Design, by David Harris, James Stine Ph.D., Sarah Harris and Rose Thompson.

Other CPU books we recommend:

• Modern Processor Design: Fundamentals of Superscalar Processors by John Paul Shen and Mikko H. Lipasti.
• Modern System-on-Chip Design by David J. Greaves.

When you study CPU books it is important to implement in Verilog at least some of the blocks you study. For example, you can implement a simple direct or multi-way cache, or a branch predictor, or an illustration of the Tomasulo algorithm or MESI protocols. You may discover that your theoretical understanding was not correct, or discover that your solution does not meet timing, or get some new ideas.

If you want to discuss these recommendations, you can join our regular meetups in Hacker Dojo on Sundays at 11 am. Additionally, we are going to have a guest event called Chips @ Dojo on March 5 at 4 pm.

The conclusion

A couple of months ago, one of the Verilog Meetup participants told me, “Yuri, you need to write a book”. While I am working on a long-term book project, I don’t think yet another book will drastically make people more efficient in learning Verilog, digital design and verification. The main issue with both beginners and university graduates is that people do not like to exercise. Beginners like infotainment but figuring out why a signal becomes high in the wrong clock cycle is kind of boring. The truth of the matter is: without going through it, a learner has no opportunity to progress to the next microarchitectural level where the fun is. Just like for a musician: unless you practice scales and etudes, there is absolutely no way you can play a Bach sonata.

This was the reason I wrote this text which combines references to existing books with links to exercises. I hope you enjoyed it unless you got bored after the first paragraph or shortly after.

Thank you,
Yuri Panchul
2026-02-13