This workshop proposal is prepared by Yuri Panchul and the Verilog Meetup community. It can be tuned to various audiences, including high-school students, college students, educators, or simply people with various backgrounds who want to understand the technology base for digital chip design and FPGA applications. The length of the workshop can vary from three hours to three days or even a week, if we are going into details. A three-hour version would probably include just exercises with Gowin/Tang FPGA boards and graphics on an LCD screen, but a three-day version may include the whole day with a discussion of ASIC implementation using TinyTapeout and eFabless.

You can join a Google group Verilog Meetup on Maker Faire to get notifications about the workshop events, as well as a Google group SystemVerilog Meetups in Silicon Valley for the weekly meetings at Hacker Dojo in Mountain View, California.

Introduction

“Verilog, ASIC, FPGA” are not exactly household words, but they are at the very heart of the microelectronics revolution that brought us smartphones, fast internet, 3D graphics and AI acceleration. For the last 40 years, the Verilog hardware description language has been used to design the logic of chips. An ASIC (Application Specific Integrated Circuit) is the chip itself, and an FPGA (Field Programmable Gate Array) is a chip used to prototype an ASIC. During the workshop, we are going to expose the students to the following concepts:

1. The difference between programming and logic design using hardware description languages.
2. The design flow for the fixed chips made in a semiconductor foundry (RTL-to-GDSII) and the flow used for reconfigurable logic, Field-Programmable Gate Arrays (FPGAs).
3. The concepts of combinational and sequential logic, logic gates and-or-not and the state elements, D-flip-flops. How to express an algorithm using these primitives. The influence of physical delays on the design organization.
4. The idea of CPU: a circuit that runs the programs. The concept of architecture (the instruction set, an interface to software) and microarchitecture (the hardware organization).
5. How the design process in electronic companies is organized: the team, the chip design cycle and the tools.

Setup

The learning process will be centered around practical exercises with FPGA boards. We can support more than 35 boards with Verilog Meetup examples, however, for the proposed seminar, we plan to use the setup that includes a Tang Nano 9K board with Gowin FPGA, a 4-inch LCD screen, a TM1638-based interface module and five female-female jumper wires. We will use Gowin EDA software running under Windows or Linux. We will provide the boards and bootable SSD drives with Linux. The participants need to bring their laptops or can use computers provided by the hosting university.

The instructions on how to setup Gowin EDA software, assemble a board set and run the examples:

GOWIN EDA Quick Start Guide V6

TangNano9KBoardSetupV3

Tang Nano 9K Synthesis and Configuration V6

 

Activities

1. Basic exercises with buttons, LEDs and a seven-segment display: and/or/not/xor gates, multiplexors, counters and shift registers. The participants will change the design in SystemVerilog, synthesize the code, upload the FPGA board configuration and see how their changes affect the behavior of the design on the board.
2. Drawing static and moving pictures on a color LCD screen or an HDMI display by changing the SystemVerilog code that computes a color RGB (red/green/blue) using X and y coordinates provided by an LCD or HDMI controller.
3. Watching demos of FPGAs used to recognize music notes, generate sounds and control the ultrasound distance measuring device.

Schedule

The general schedule for a one-day seminar:

10.00-11.00. A lecture on the concepts of hardware description languages and register transfer design methodology.

11.00-12.00. Exercises with FPGA boards and combinational logic using buttons, LEDs and seven-segment display: logic gates, multiplexor, displaying letters on 7-segment display at different positions.

12.00-13.00. Exercises with FPGA boards and combinational logic using an LCD screen or HDMI monitor to display graphics: rectangles, ellipses, a parabola, a hyperbola, and repetitive patterns.

13.00-14.00. Lunch break

14.00-15.00. Sequential logic. A short lecture following with the exercises with the FPGA boards using buttons, LEDs and a seven-segment display: D-flip-flop, counter and shift register.

15.00-16.00. Creating moving pictures on a graphics screen using sequential logic. We modify the graphical examples with created earlier by adding counters and control with keys. The goal is to create a simple graphical game.

16.00-17.00. Conclusion. Demos of sound recognition, sound generation, discussion of RISC-V processor design and jobs in the electronic industry.

Extensions

There are three directions we can extend the seminar:

1. Discussing CPU: the idea of architecture and microarchitecture. Computer architecture is the software side of the CPU: the instruction set and assembly programming. Processor microarchitecture is the hardware side: the structure of the CPU pipeline and the computational blocks.
2. Discussing microarchitectural problems the intern candidates get during interviews in electronic companies.
3. A step-by-step instruction on implementing the design in ASIC using TinyTapeout infrastructure and eFabless partnership with Skywater silicon foundry. This is an affordable way for a group of students to put their ideas into working silicon.

In addition to this workshop proposal, we are working on a hackathon proposal in which the participants prototype graphical games on Gowin FPGA boards, present them to a panel of judges and gamers, and finally implement the games in ASIC using TinyTapeout and eFabless. The games will be primarily judged on how cool they are; however they must pass all the technical criteria, including the absence of verilator lint warnings and no negative slack in static timing analysis for both FPGA and ASIC implementation. We also intend to restrict the games in size (like up to 4 TinyTapeout tiles) and prohibit the use of CPU cores in the design (otherwise, the competition will be dominated by retrocomputing fans bringing back to life their favorite games from the 1980s). The focus of the competition should be on how much fun you can get from clever hardware design rather than from software (which already has a lot of competitions).