Learning digital design is similar to learning to play a flute or going to the […]
Category: articles
A new challenge for the startups working on AI-generated UVM testbenches
One of the startups working in the AI for Verilog area contacted me with the […]
Learning HDL without worrying about the toolchains
Learning HDL without worrying about the toolchains The FPGA setup and configuration problem Learning Verilog […]
Interfacing with Digilent PmodALS on an FPGA
Ever wanted to work with an ambient light sensor and have it work on an […]
Verilog Meetup: the current and proposed projects as of 2025-12-25
1. The current needs in FPGA board support Altera: Terasic DE23-Lite. This is a new […]
Reviewing the output of an AI EDA tool that generates SVA
Abhishek Varma, MS in VLSI & Microelectronics, from Illinois Institute of Technology, created an AI […]
An update on soldering recommendations, with a video
Some FPGA boards are sold with unsoldered headers. Examples include Tang Nano 9K with Gowin […]
A push for better workforce development in EE starts with the Verilog Meetup at Cal Poly San Luis Obispo
The idea to make a Verilog Meetup event at California Polytechnic State University, San Luis […]
Moving your design from FPGA to ASIC using Verilog Meetup variant of the Tiny Tapeout template
The coming Verilog Meetup at Cal Poly SLO will include an FPGA hackathon with a […]
Verilog Meetup at Cal Poly San Luis Obispo, California on October 25-26
The meetup location is planned for Advanced Technology Laboratories on Cal Poly’s main campus in San Luis […]
Photos from Maker Faire Bay Area 2025 in Vallejo, California
Maker Faire is a kind of mini-Burning Man for the hobbyists of all kinds, however […]
Verilog Meetup project status as of 2025-08-28
The current activities: book, manual, seminars in California, seminars internationally, board support etc: One-liners: Writing […]
Samsung expands GPU team: open RTL Designer and Performance Architect positions
The team at Samsung that designs the Xclipse GPU in Galaxy phones with Exynos SoC […]
Separating the wheat from the chaff in AI-driven EDA startups
Not all AI entrepreneurs are the same. There are good guys who make prototypes of […]
Photos from the OpenSauce event, and looking forward to the Maker Faire
OpenSauce is an atypical event, a sort of school science fair for the (mostly) adult […]
An update on the FPGA board setup convenient for the hackathons
We made an update of the pin assignments for the board configuration described in the […]
Verilog Meetup on Open Sauce 2025: Learn Chip Design by Making Games on FPGA
Verilog Meetup on Open Sauce 2025: Learn Chip Design by Making Games on FPGA Ever […]
В клубе “Синергия” в Сакраменто: Игры на платах ПЛИС как введение в работы в микроэлектронике
В субботу 7 июня, с 14.00 до 17.00, в клубе “Синергия” в Сакраменто, Калифорния, пройдет […]
How to Fail Those Students Who Rely on ChatGPT
We at Verilog Meetup constructed an exam/interview problem that has an interesting property: if a student tries to figure […]
The Armenia Opportunity: EDA, ASIC, FPGA + connections with USA, China and Russia
The winners and organizers of the FPGA Hackathon on EDA Connect conference in Yerevan, Armenia […]
Students in Tijuana, Mexico went through a 1 1/2 day marathon in doing Verilog exercises on Gowin FPGA boards
Some highlights from the Verilog Meetup workshop we did at Universidad autónoma de Baja California […]
Instructions for Verilog Meetup examples are now available in 5 languages: English, Spanish, Russian, Ukrainian and Belarusian
Instructions for Verilog Meetup examples are now available in 5 languages: English, Spanish, Russian, Ukrainian […]
A new edition of SystemVerilog-Homework adds exercises that use FPU of an open-source CPU
The industry needs interns trained in pipelined microarchitecture and timing, with solid coding skills Every […]
Credit-Based Flow Control
Flow control is a crucial synchronization technique for data transmission. It ensures the efficient flow […]
Verilog Meetup events in Mexico and Armenia
The dates for the Verilog Meetup events in Mexico and Armenia are set: Friday and […]
The State of Caravel: the First Look
The State of Caravel: the First Look Yuri Panchul, 2025.01.22 This text is a mix […]
Follow-up letter to the attendees of the Verilog Meetup booth at Maker Faire 2024 in Vallejo, California
Thank you for attending the Verilog Meetup booth at Maker Faire. We decided to write […]
Between Physics and Programming: a Workshop on a Hardware Description Language SystemVerilog used to design the silicon chips
This workshop proposal is prepared by Yuri Panchul and the Verilog Meetup community. It can […]
Notes on using basics-graphics-music repo under Linux and Windows
The Git repository of introductory Verilog examples, basics-graphics-music, uses Bash scripts for all user operations […]
How a chip is designed: the technology, team and jobs – Как проектируется микросхема: технология, команда и работы
On Saturday, August 31, we are going to have an electronic education event in Los […]
Maria soldered her first pin and you can do that too!
The is a newer version of this article: An update on soldering recommendations Maria, an […]
Philip Sisa M, A member of Verilog Group
My name is Philip Sisa M, having worked in telecommunication industry for more than 8 […]
Can Gowin beat Xilinx and Altera in the educational market?
Gowin Semiconductor is at the Sensors Converge exhibition in Santa Clara today. I went to […]
Andrea Guerrieri, an co-author of HLS tools and ARM SoC textbook, gave feedback about Verilog Meetup materials
Today, I met Andrea Guerrieri, a researcher from Switzerland, at the Design Automatic Conference (DAC) […]
A new platform for FPGA seminars based on Gowin Tang Nano 9K: adding sound, graphics and microarchitecture labs
Gowin has clear advantages over Xilinx in the educational FPGA board market: Gowin boards are […]
Beginner’s guide to Basic-graphics-music examples
Beginner’s guide to Basic-graphics-music examples These are examples to demonstrate labs sessions for systemverilog-homework which […]
A Case Study on Effective Pipeline Design in Digital Systems
Throughput and latency are fundamental concepts in modern digital system. Throughput refers to the time […]
Focus on Microarchitecture
After interviewing a number of recent EE and CS graduates for RTL and DV positions […]
Bootstrapping Azerbaijan as a new center of ASIC design + Verilog Meetup #6 in Silicon Valley
Last week I was doing a seminar on SystemVerilog, ASIC and FPGA at ADA University […]
Self-education and educating others
The first meetups of the Portable SystemVerilog Examples group at Hacker Dojo in Mountain View, California were a […]
Why would a software engineer attend an FPGA hardware meetup at Hacker Dojo?
For the last 30 years digital chip design is not done by schematic entry anymore: […]
Toward the January meetup on portable SystemVerilog examples in Silicon Valley
The team developing a set of portable SystemVerilog examples decided to organize the first event in Silicon […]
The first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA
Need to start your career or hobby in digital design and verification of silicon chips […]