Armenia is a lucky country. Back in the 1990s somebody lobbied Synopsys, the #1 leader in the Electronic Design Automation market, to create a division there. It was joined by Mentor Graphics / Siemens EDA, another EDA leader, then NVidia. Synopsys Armenia became the largest Synopsys division outside the US Silicon Valley and Boston, although the Taiwanese may tell you otherwise. Since Synopsys and Mentor make software used by chip designers in Apple, Samsung, AMD and all other electronic companies, Armenia has an unfair advantage over all their neighbors in Caucasus and Central Asia.
In addition, Armenia has friendly relations with Russia, and most Armenians speak Russian as well. This has facilitated the move of some Russian companies to Armenia, for example, a RISC-V semiconductor IP provider Syntacore. Finally, as we can see from the recent conference EDA Connect, Armenia is attracting the attention of electronic and EDA companies from China.
EDA Connect featured not only academic and industrial papers but also a hackathon on FPGA design, attended by local students from Yerevan State University, the American University of Armenia, the Russian-Armenian University, the French University in Armenia and others.
A director from Siemens EDA, Sedrak Sargsyan made a speech about the history of EDA, Electronic Design Automation. Then he discussed 3D chips and ML:
Here is Sedrak Sargsyan’s slide about the reasons EDA took root in Armenia:
The R&D director of Synopsys Armenia discussed the role of Synopsys EDA tools in making the giant chips to accelerate AI training:
Yu Huang, a researcher from China, made a presentation about using AI for EDA, siting Synopsys as an example:
Peter Coveney, a professor from University College London, shared his experience about using supercomputers for biotechnology, like developing new drugs. In addition to this presentation, I noted a poster about a supercomputing project in Armenia:
Another presenter from China, Yunsheng Zheng, described the Chinese EDA community and a conference he organizes:
After lunch, the participants split into two rooms: one for the industrial section and another for the educational section. I had a presentation in the educational section aimed at students:
Below are a couple of slides. You can see all the slides here and a video. The researcher on the left of the first slide is Lilia Kirakosyan from Russian-Armenian University. Lilia is specializing in SDR, and she helped me with the FPGA hackathon:
An example interview problem I mentioned in the presentation is a pipelined block that computes a formula with dependencies, such as √(a + √(b + √c)). Besides this presentation, I also wrote a post about it and a follow-up post.
Some background on the problem in the education system we are trying to solve:
Verilog Meetup, an open-source initiative, helped to connect the education in more than 30 universities to the industrial needs
Any person who interviews students for positions in a chip design team knows there is a significant gap between what they learn in school and what the industry needs from them. The graduates usually know some Verilog, can write an FSM, answer a question about STA, explain the 5-stage MIPS / RISC-V pipeline or Tomasulo algorithm. However, many students struggle in important areas, such as organizing data processing pipelines with dependencies and flow control. This know-how is essential to work in diverse areas: networking, where you have to process a stream of packets coming back-to-back with backpressure from time to time; GPU, where you process a stream of colored triangles in fixed function blocks in the same way; interconnects, where you process a stream of memory read and write requests; and so on.
In addition, even the graduates from top US schools are rarely trained in functional verification and performance modeling. They don’t know how to test their RTL designs against transaction-based models. As a result, they miss corner cases or create microarchitectures with poor bandwidth.
Some companies use commercial trainers or verification courses from the tool vendors to train newly hired college graduates. However, such training is usually centered to teach a language (SystemVerilog), a library (UVM) or a specific simulation or formal verification tool. The main challenge for the recent graduates is usually in a different area: they lack practice verifying pipelined and out-of-order microarchitectures.
The teaching of physical design can be improved as well. Currently, most students do not develop intuition about the static timing analysis and do not know how to solve a negative slack problem. There should be exercises that balance latency and timing.
We at Verilog Meetup are taking steps to improve the curriculums by offering teachers two open-source repositories: basics-graphics-music that contains introductory examples for more than 30 FPGA boards, with ASIC RTL-to-GDSII integration path; and systemverilog-homework, a set of problems that start from zero and proceed to the level of job interview questions on microarchitecture.
We had presentations in two rooms, including:
- Three presentations from Siemens Armenia focusing on mechanical and thermal aspects of 3D chips and the Mentor Calibre tool.
- Three presentations on system-level design by Armenian developers from ProximusDA, Instigate Design and Instigate Research.
- Three presentations on RTL design flow and functional verification by the researchers invited from Russia. One presentation was on Utopia EDA, an open source logic synthesis tool, another was on SVAN Static Analysis tool and the third one on UVM-based verification.
Instigate is a group of companies in Armenia that include a startup incubator, a research center and several service and product companies in EDA and Design IP. There are approximately 700 people involved. They are doing custom projects for such companies as Microchip / Microsemi and Xilinx / AMD. It is possible to meet Instigate people on Design Automation Conference in San Francisco:
Proximus is a spinoff of Instigate. They created an EDA product in the area of system-level design that allows to map computations into a heterogeneous system that consists of CPUs, GPUs and FPGAs. They connect these components using FIFOs, both hardware and software-based. They run a high-level simulation and profiling of the system assuming that FIFOs have infinite depth. Based on the simulation, a user can determine the actual FIFO usage and figure out some practical depth that does not limit the bandwidth. Proximus offers this product and uses it themselves for their service contracts.
This reminds me of CoWare, a company acquired by Synopsys a while ago. Except CoWare concentrated on system-on-chip designs and did million-dollar service contracts with such customers as Sony, while Proximus does higher level system design, implementing many components in software that run on CPU and GPU.
While Armenian researchers focused on the system-level and physical-level, the invited Russian researchers covered things in the middle, the front-end register-level design and verification. Russian synthesis tool Utopia EDA goes along the same lines as Yosys, ABC, OpenLane, OpenROAD and other open-source ASIC design tools from Austria, University of California UC Berkeley, UC San Diego and other FOSS EDA places. Such tools can be used in several domains:
- To train university students to develop the industrial EDA tools;
- To provide an alternative to Synopsys and Cadence in some niches, for example in microcontroller and IoT ASIC design;
- To provide an open source solution for FPGA design, particularly for Gowin and Lattice FPGA.
I made a video of Utopia EDA presentation:
SVAN from ISPRAS is competing against Synopsys SpyGlass and similar linters. I took a photo picture with Alexander Kamkin, a developer of Utopia EDA and with Ruben Buchatskiy and Yan Churkin, the developers of SVAN:
The presentation about SystemVerilog / UVM verification was from Sergey Chusov, from the National Research University of Electronic Technology, a Russian university in Zelenograd. Zelenograd is the Russian Silicon Valley; it is a suburb of Moscow that has two fabs (Mikron and Angstem), a number of semiconductor design companies, and this university, also known as MIET.
A UVM presentation from Sergey included a broad introduction to the subject and a discussion of a specific library feature, the object factory to mutate the verification environment. MIET is ahead of most American universities in teaching SystemVerilog-based verification. This topic is not considered important even at Stanford; as a result, the US students typically don’t know how to verify a microarchitecturally challenging design, even a design of their own.
Sergey Chusov teaches not only in MIET, but also at Digital Circuit Synthesis School, an initiative to improve the curriculum in 25 Russian and 2 Belarusian universities. We had a dinner two other engineers who help to prepare SystemVerilog-Homework and came from Russia to Yerevan for EDA Connect: Maxim Kudinov and Maxim Trofimov:
On the second day, we held a hackathon using FPGA boards. The hackathon’s goal was to create a graphical game — not by writing a program that runs on a processor, but by configuring a digital circuit inside the FPGA, synthesized from code written in the hardware description language SystemVerilog. Additionally, we aimed to port the game into the TinyTapeout environment, which allows you to order your own ASIC chip from a factory at a relatively low cost.
On the day before, we taught the students what SystemVerilog and FPGA are, following the same program I had tested a month earlier during a two-day seminar in Mexico, which itself grew out of my experiments with visitors at the Maker’s Faire exhibition in California.
At the end of the first day and the beginning of the second, we went through an example of a game on an LCD screen where a user-controlled object knocks down another object, all managed by a finite state machine. You can interpret this as a “Ship and Torpedo” or “Drone and Missile.”
While our example infrastructure supports multiple vendors (Xilinx, Altera, Gowin, Lattice), we used the boards with Gowin FPGAs. Gowin EDA synthesis is much faster than Xilinx Vivado and faster than Altera Quartus. Gowin boards are inexpensive, high quality and compatible with convenient color LCD screens. For more details, see Can Gowin beat Xilinx and Altera in the educational market?
Forty-two people signed up for the hackathon, and the second-day attendance was around thirty. Some people participated only in training during the first day. In the end we had ten projects:
Some projects. This engineer earned an extra point because she integrated an ultrasonic rangefinder with the board, using it as a random number generator to introduce some randomness into the movement of the figures on the screen:
A student connected a microphone to the board and displayed musical notes on the screen:
On the first day another student asked me about the evaluation criteria. I responded: “mostly aesthetic, although there will also be some technical aspects, such as synthesizability with TinyTapeout and the absence of negative slack”. So the student created something picturesque, with the trees, clouds and hopping animals.
Some students created variations with three objects while other students created the whole swarms of objects:
One project was created by a group of students. This is how we create large semiconductor IPs in the electronic companies, by dividing functionality between many engineers – this is an art in itself:
During the hackathon most participants used Simply Linux distribution from a bootable SSD. However, you can setup all the necessary software (Gowin EDA, openFPGALoader, Git, Bash, VSCode) on most other Linux distributions, as well as under Windows and Mac with Apple Silicon. Under Windows you can choose to setup either under “regular” Windows or under WSL2 (Windows Subsystem Linux). See the instructions (although the pin positions on the diagram has to be updated – I swapped the pins for GPIO and sound DAC recently).”
There was a request on how to setup everything on Apple Mac M1-M4. I wrote a short instruction:
# Instructions for setting up on Apple Mac:
# find Gowin EDA Download,
# look to the tab “Software for Linux”,
# download “Gowin V1.9.10.03 Education (Mac)”.
cd ~/gowin cp ~/Downloads/Gowin_V1.9.10.03_Education_m
tar -xvzf *.tar.gz
sudo xattr -rd com.apple.quarantine IDE Programmer
cd ~/projects
git clone https://github.com/yuri-panchul/basics-graphics-music.git
cd 2025_02_21_tijuana/day_2_pm_graphics_usi
cd 2_game_example
./03_synthesize_for_fpga.bash
The award ceremony:
The bottom line: I expect EDA Connect to continue; it is a convenient way to run tutorials and connect companies and universities from Armenia, USA, China, Russia, and Europe. In the aftermath of the event I also discussed with Instigate and Russian-Armenian University an idea to create an FPGA board set with a book that provides step-by-step instructions and some necessary theory for three target audiences:
- Hackathons for high school and college students
- Introductory digital design and computer architecture classes
- The graduating students who aim to prepare for job interviews
The cost of the basic set is around $25, the cost of extended is under $40, here is a spreadsheet with all the components.
