Gowin Semiconductor is at the Sensors Converge exhibition in Santa Clara today. I went to their booth yesterday and met the team: CEO Jason Zhu, sales, marketing and application engineers. We discussed the topic of the educational boards used for EE classes, such as 6.111 at the Massachusetts Institute of Technology (MIT). Every ASIC designer working at Samsung, Apple, NVidia and similar companies has taken a similar class back in school. It is not possible to train an RTL designer using a Verilog simulator only. In order to develop intuition in static timing analysis (STA) and how many resources are inferred for a given RTL code, a student has to either use FPGA or ASIC synthesis, and with FPGA, he also gets the benefit of working with an actual design.

This fact makes educational FPGA boards a critical technology for any country’s high-tech workforce development, a topic that now concerns even the US Government, as I heard at the Design Automation Conference in San Francisco a day earlier. For a good reason: the current EE and CS students are not sufficiently trained in RTL and microarchitecture.

Gowin has an opportunity to grab this market from Xilinx and Altera. For two reasons: 1) price and 2) synthesis speed. Synthesis in Gowin IDE runs an order of magnitude faster than on Xilinx Vivado. A design of a graphical game with sprites is synthesized in 209 seconds with Xilinx Vivado and just 22 seconds with Gowin. Altera is in the middle: 56 seconds. If you are a student working on a project, this is a big deal, since you run synthesis with every code change, and if you do this 20 times a day, waiting minutes instead of seconds is annoying, and Gowin IDE speed gives a totally different user experience.

Now let’s discuss what do we need for an educational FPGA board.

First, we need an FPGA that can fit the designs up to the size of an educational RISC-V CPU with 3 or 5 pipeline stages. This can be accommodated with 6K-10K FPGA cells. Ideally, we want to have enough capacity to accommodate several CPU cores, if we want to demonstrate three CPU cores sharing a common memory. Eventually, we need to fit a midrange CPU with TLB MMU, capable of running Linux – this would require a bare minimum of 20K Altera cells, but this can wait until more advanced classes. In other words, we can have two boards with different prices and capacities for introductory and advanced courses.

What kind of peripherals do we need on an educational board besides buttons and LEDs? A wide 8-digit 7-segment display is convenient for showing the registers of a CPU or microarchitectural features like a FIFO. What else? Let’s look at MIT site “6.111 Memorable Projects”. We can see a list of projects that use graphics and sound. For this reason, before meeting with Gowin on the show, I assembled the following setup, using Tang Nano 9K board, a TM1638-based interface module, an LCD display, a microphone and I2S sound output. I wrote a separate post that lists the used components, and you can see the .cst file that defines the pins and the Verilog wrapper that shows the pin usage in the example repository.

To accommodate designed larger than 9K Gowin cells, I also created a setup with a Gowin 25K cell FPGA:

I discussed the setups and gave one of them to Professor Andrea Guerrieri from École Polytechnique Fédérale de Lausanne. Professor Andrea Guerrieri is a co-author of the textbook “Fundamentals of System-on-Chip Design on Arm Cortex-M Microcontrollers” by René Beuchat, Andrea Guerrieri and Sahand Kashani, written in collaboration with ARM. Professor Guerrieri is willing to review our Verilog Meetup examples and help us with his students to extend them:

I also discussed this setup and the examples with Professor Rafael Aroca from Universidade Federal de São Carlos, Brazil. Professor Aroca came to the United States to attend IoT Tech Expo North America and stop by at our Verilog Meetup in Mountain View.

Professor Aroca has his own board created based on Tang Nano 9K with Gowin FPGA:

However, the features of the ChipInventor board do not match our needs for Verilog Meetup examples. Jason Zhu suggested working with the Chinese board suppliers to design a well-balanced board and we believe it can be a hit in educational market. If you want to take part in specifying the requirements, preparing the examples, organizing the seminars, hackathons or events, you can come to Verilog meetups at Hacker Dojo in Mountain View, California. We have them every Sunday from 11 am to 2 pm. If you are unable to come to Mountain View, you can join us online over Zoom at the same time. Please send email to info@verilog-meetup.com, join Google Group meetsv and Telegram channel verilog_meetup to introduce yourself and get started.

We are looking forward to work with Gowin team and see them at next shows: