Chips @ Dojo 2026 was a guest event at Hacker Dojo in Mountain View, California, with colleagues from the UK, focusing on progress in open-source silicon design and verification tools. What we covered:
* The UVM Breakthrough: How we ported 50+ production UVCs and codified 35+ non-obvious failure modes into AI guardrails.
* The Python Alternative: Andrew Bond (Axelera AI) dives into AVL, showing how Python-based verification is ready for production.
* The Cloud-Native Compile: A look at AWS Economics—the real-world price-to-performance mapping for scaling Verilator in the cloud.
* The SV Core: Yuri Panchul breaks down advanced SystemVerilog techniques and the bridge to open-source synthesis with Yosys.
Some pictures and the recording:
Srinivasan Venkataramanan, the CEO & Founder at AsFigo, with Yuri Panchul, a GPU RTL Engineer from Samsung Advanced Computing Lab and the founder of Verilog Meetup at Hacker Dojo.
The event was visited by David Harris, a co-author of several textbooks, including:
- Digital Design and Computer Architecture, RISC-V Edition by Sarah Harris & David Harris.
- CMOS VLSI Design: A Circuits and Systems Perspective by Neil Weste and David Harris.
- RISC-V System-on-Chip Design by David Harris, James Stine Ph.D., Sarah Harris and Rose Thompson.
Yuri Panchul and David Harris at Samsung Electronics offices on the same day as a Chips@Dojo seminat at Hacker Dojo:
The recorded video:
It was wonderful experience working on Open spice Silicon design Verification and porting UVC’s with Verilator. Felt extremely happy to work with Srinivasan and Ajeetha Kumari