How different are the jobs of an FPGA designer and an ASIC designer? Both write Verilog RTL but there are little differences. Below is my list; feel free to add to it, but only if you have a first-hand experience on the subject. I am not interested in AI output, only the authentic human discussion.
1. Memory. An FPGA designer uses the internal BRAM memory and the external off-chip memory, such as SDRAM. An ASIC designer is primarily concerned with embedded SRAM memories. He uses memory compilers to build logic memories out of physical memory blocks, specific for a given technology. Such memories differ not only in width and depth, but also in the number of ports (single, dual, pseudo-dual), latency and memory protection using ECC.
An ASIC designer has to define such memories early in the design cycle, when he writes a microarchitecture specification for his block. He needs to decide whether any given FIFO is flop-based or SRAM-based, based on power data from a memory compiler and some rules of thumb which are somewhat different for each company and technology node. The defined memories are given to the physical design (PD) team, together with the designer’s thoughts on sub-block connectivity. This information allows the PD team to sketch a floorplan early.
2. Clock gating. Power consumption is less of a concern for most FPGA designers, but is very important for ASIC projects. A large chip, such as a chip in a core router or AI accelerator, can consume hundreds of watts. If a designer does not pay attention to the power on each level, the chip may require liquid cooling. A mobile chip has to survive a day on a single battery, an IoT sensor in a smart agriculture application has to work in a field for a season, measuring soil chemistry and transmitting data to the hub.
The most important low-power techniques necessary for a front-end ASIC designer are: 1) using enables for fine-grain clock gating; 2) using busy signals and sub-block-level clock gaters for mid-grain clock gating, and of course 3) microarchitectural techniques, such as using ring buffers instead of shift registers, which reduces switching.
3. Arithmetics. If you get Verilog source for a typical CPU designed for ASIC, and synthesize it for an FPGA, you are likely to discover a significant drop in clock frequency. For example, a 1 GHz ASIC core may be able to run on an FPGA only at 50 MHz. To counteract this effect, FPGA vendors include optimized arithmetic blocks, such as Xilinx DSP48. The FPGA designer has to be aware of such blocks and use them explicitly to achieve higher frequency, like 200 MHz or more. Note that such blocks are vendor-specific, you have to use ifdefs to port your design to Altera, Gowin or Lattice.
Overall ASIC projects have more elaborate verification and modeling teams (in addition to already mentioned PD team), but this is a topic of a separate post. All these differences are relevant not only to individuals who explore their career options, but also to business people who want to assemble an ASIC design team from algorithm specialists and FPGA designers. In principle this is doable, especially if such team outsources all PD-related activity to silicon services companies such as VeriSilicon. However the designers have to be aware of ASIC differences and plan ahead.
