Verilog Meetup at Cal Poly San Luis Obispo, California on October 25-26

The meetup location is planned for Advanced Technology Laboratories on Cal Poly’s main campus in San Luis Obispo. Unless there is a sports game or other event on the weekend of October 25/26, parking at Parking Lots H12, H14, and H16 is free on weekends.

The goals for the Verilog Meetup at Cal Poly SLO:

1. Introduce the basic technologies of digital chip design to a wider audience than EE students. It includes students who are choosing a career path or simply curious about neighboring areas, such as a software student who wants to build an FPGA-based hardware accelerator for his project.
2. Help the graduating students to train themselves for job interviews, particularly in the areas of SystemVerilog and microarchitecture. These areas are key to job success for a front-end RTL designer in an electronic company.
3. Discuss how the current EE and CS curricula can be improved in the area of register transfer level (RTL) microarchitecture, design verification and EDA vendor independence.

Organizers and presenters: Yuri Panchul, Ramprakash Baskar, Alex Huang

October 25, 2025 – Tutorials

10 am – 11 am. An express tour over the basic ideas of the digital design methodologies that brought us smartphones, fast internet, 3D graphics and AI acceleration. Hardware description languages, RTL-to-GDSII design flow, implementing algorithms using combinational and sequential logic, static timing analysis (STA), Application Specific Integrated Circuits (ASICs) for mass production, and Field Programmable Gate Arrays (FPGAs) for prototyping, special applications and education.

11 am – Noon. Hands-on labs with FPGA boards from multiple vendors to get a feeling for the technologies described during the express tour. The vendors include Xilinx, Altera, Gowin and Lattice. Starting with gates, muxes, buttons and LEDs, continuing with drawing graphical images on LCD and HDMI screens.

Noon – 1 pm. Lunch.

1 pm – 2 pm. The basics of CPU. Simulating RISC-V on the architecture level, simulating a single-cycle core on register-transfer level (RTL), and synthesizing the core for FPGA and ASIC. A brief discussion of the CPU IP market and different niches for low-power, mid-range, multithreaded and superscalar cores. Mention of the coherent clusters, AI accelerators and heterogeneous systems.

2 pm – 3 pm. Basics of microarchitecture, the level of abstraction above the register-transfer level. Data processing pipelines, FIFO, control flow, memory banking and their applications to building custom computing blocks for GPU and networking.

3 pm – 4 pm. Other presentations:

• Moving the designs from FPGA to Tiny Tapeout, an open-source ASIC design infrastructure. A good way to study max frequency versus area in ASICs. Tiny Tapeout allows you to get your own chip by ordering it through the MPW (Multi-Project Wafer) service.
• Music and sensors. Sound recognition and generation, serial protocols using I2S as an example.
• How the process of a chip design in an electronic company is organized. The cycles of a chip project, the interactions of different departments: technical marketing, architecture, RTL design, verification, physical design, post-silicon debug and others. Organization of the project into block teams and the whole chip team, and the related topics.

October 26, 2025 – Hackathons and mock interviews

10 am – 11 am. A presentation “Removing the vendor lock from the digital design labs on FPGA”. We present an infrastructure that allows running a set of SystemVerilog lab examples unchanged on 46 FPGA boards from all the major vendors: Xilinx, Altera, Gowin and Lattice. This infrastructure is implemented in a repository basic-graphics-music (BGM).

The methodology allows isolating a student from the specifics of a board and a toolchain and concentrating on the things that matter: SystemVerilog language, RTL design methodology, static timing analysis (STA) and microarchitecture. This is accomplished by using scripts, wrappers and parameterization. An educator can easily switch from one board to another, one vendor to another or even use a mix of boards from different vendors during the same class.

As a part of the presentation, we will explain how to add support for a new board or a new toolchain to the project.

11 am – Noon. A presentation “The Limits of AI in SystemVerilog Microarchitecture”. We present a set of microarchitecture challenges that were used both for screening the students for job referrals and benchmarking AI engines in two large companies and two EDA AI startups, together with the methodology to verify the answers to these challenges.

Noon – 1 pm. Lunch.

1 pm – 4 pm. Three hackathons:

1. Games and sensors.Participate in a hackathon to create hardware-only graphical games on FPGA boards. The games will be primarily judged on how cool they are; however they must pass all the technical criteria, including the absence of verilator lint warnings and no negative slack in static timing analysis for both FPGA and ASIC implementation. We also intend to restrict the games in size (like up to 4 TinyTapeout tiles) and prohibit the use of CPU cores in the design (otherwise, the competition will be dominated by retrocomputing fans bringing back to life their favorite games from the 1980s). A game may incorporate peripheral devices such as a joystick or an ultrasonic distance measurer.
2. Adopting a board.Adding support for a new board or a new toolchain to the basics-graphics-music (BGM) example set. We are going to have a large collection of boards and you can choose one of them to work on. Since Cal Poly San Luis Obispo is working on adding Microchip / Microsemi / Actel boards into the classes, we can use these boards for our hackathon as well (assuming we have such boards during the event).
3. A mock interview.You will get a set of micro-architectural questions similar to those used in a job interview at an electronic company. Some questions require drawing microarchitectural diagrams, others require writing code, or both.

The meetup location: