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Month: January 2026

A new challenge for the startups working on AI-generated UVM testbenches
articles

A new challenge for the startups working on AI-generated UVM testbenches

January 20, 2026January 20, 2026 by Yuri Panchul

One of the startups working in the AI for Verilog area contacted me with the […]

Learning HDL without worrying about the toolchains
articles

Learning HDL without worrying about the toolchains

January 4, 2026January 4, 2026 by Andrew DeKelaita

Learning HDL without worrying about the toolchains The FPGA setup and configuration problem Learning Verilog […]

Interfacing with Digilent PmodALS on an FPGA
articles

Interfacing with Digilent PmodALS on an FPGA

January 4, 2026 by Huaxuan (Jason) Yang

Ever wanted to work with an ambient light sensor and have it work on an […]

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