Reviewing the output of an AI EDA tool that generates SVA

Abhishek Varma, MS in VLSI & Microelectronics, from Illinois Institute of Technology, created an AI EDA tool that generates SystemVerilog Assertions (SVA).  Yuri Panchul asked Abhishek Varma to run his tool on his open-source SystemVerilog example of an AXI-Lite Verification IP that contains a master BFM (Bus Functional Model) and a reference slave.  In video below Yuri reviews the results of Abhishek’s tool run. This video also might be useful for those who want to learn AXI protocol, especially its valid/ready handshaking, pipelining and out-of-order with tags feature.