The coming Verilog Meetup at Cal Poly SLO will include an FPGA hackathon with a twist: the participants get extra points for moving their design into an ASIC using a variant of the Tiny Tapeout template. The reference design is not just a few gates: it includes interfaces to the graphical display and a microphone, so even beginner students can design something artistic. We encourage the participants to try this flow before the event, for two reasons:
- We would like to use the seminar time efficiently, discussing the SystemVerilog language, RTL design, and pipelined microarchitectures. We don’t want to spend an hour teaching how to use GitHub and moving from student to student with troubleshooting.
- The seminar would benefit from extra review and quality assurance of the materials before the event.
Here are instructions on how to do it. If you do not see all the images, try pressing F5 to reload the web page:
Log in to GitHub. Go to https://github.com/verilog-meetup/ttsky-verilog-template-for-verilog-meetup and press the button “Use this template”. If you do not see the button, it is likely that you have not logged in.
Fill the form and press “Create repository”:
This is what the created repo should look like:
Note the file lab_top.sv in src directory. This is the top user module and it is compatible with our FPGA-based infrastructure basics-graphics-music (BGM); no changes are necessary to port this code from FPGA.
The rest of the files in src directory is glue logic and the modules to support the peripheral devices: TM1639-based interface module, VGA display and INMP441 microphone.
Set the permissions to run the actions: synthesis, simulation, preparing the PDF doc:
Set the pages for the actions. This is what you may see before setting the pages:
Select “GitHub Action”. After setting the pages:
When you go to the Actions tab the first time, you may see the following message. Press “I understand my workflows”:
Now you should see the actions running:
The actions should be done within 10 minutes or so. If it took more than 30 minutes, something is wrong:
If you don’t set the pages right, you will see the following error. Please revisit Settings|Pages|Source and select “GitHub Action”.
If you get any errors, they are most likely due to permission and page settings. Review them and manualy re-run the actions:
Do not try to manually run the fpga action. This action, derived from the original Tiny Tapeout template, is not compatible with the Verilog Meetup FPGA examples, a source of lab_top.sv module. To synthesize those examples for FPGA you need to clone basics-graphics-music (BGM) repository to your computer system and use Bash scripts inside the labs directory of the repository tree.
Click on the GDS action results:
Scroll down to the cell usage:
Scroll to the end to see the created artifacts. Download the rendered image:
Unzip the GDS rendering image. This is how it should look like:
Download the flow logs:
Find the log for the Static Timing Analysis (STA) summary:
Find the log with the STA critical paths:
Now you can modify the repository code. Get the cloning URL:
In a terminal, run “git clone”. If you don’t have experience with Git and don’t have Git on your system, google how to install it:
You can try modifying the Yaml file with the project information:
For example you can try to see if the design fits one tile rather than two tiles:
Check the differences caused by your changes, then commit and push:
Your push should trigger synthesis and other actions in your repository on GitHub:
We got an error:
Apparently the design does not fit one tile, we need at least two:
If you choose to submit your design to Tiny Tapeout and order a board with your chip, you will need the following component to connect to a VGA monitor:
The “doc” action generates the following PDF which contains the interface pinouts to the TM1638 interface module, VGA display, I2S microphone, UART and some switches you can connect to your design:
Before submitting your ASIC design, you should debug it on an FPGA board. Our Verilog Meetup / Basics-Graphics-Music (BGM) infrastructure supports 46 boards with FPGAs from Xilinx, Altera, Gowin and Lattice:
The current Tiny Tapeout prices for two tiles of their ASIC and a demo board:
How the Tiny Tapeout board looks like:
Please try it before the seminar. If anything goes wrong, please leave a comment and I will get back to you.
Thank you!
Yuri Panchul
1 thought on “Moving your design from FPGA to ASIC using Verilog Meetup variant of the Tiny Tapeout template”
Comments are closed.