Verilog Meetup on Open Sauce 2025: Learn Chip Design by Making Games on FPGA

Verilog Meetup on Open Sauce 2025: Learn Chip Design by Making Games on FPGA

Ever wondered how a chip designer does their job? During the coming Open Sauce 2025, on July 18-20, 2025 – you can learn the basics of SystemVerilog hardware description language in a fun way by creating circuits that implement graphical games. We can show you in the Verilog Meetup booth how to use FPGA boards to prototype your designs with reconfigurable logic. We are also compatible with TinyTapeout infrastructure, which allows you to manufacture your design in an ASIC chip.

Verilog Meetup is a group working on two open-source projects that have already helped more than 30 universities worldwide enhance their digital design curricula. We create examples in SystemVerilog, a hardware description language, that work on more than 30 FPGA boards and are compatible with TinyTapeout’s ASIC design infrastructure.

We target two audiences: beginners and university graduates who need to prepare for job interviews. For the beginners, we are trying to make learning fun by connecting digital design with sound recognition, graphics and games. For those preparing for job interviews, we cover topics in microarchitecture, such as pipelining, FIFO queues, arbitration, and others, which are not fully covered in a typical university curriculum.

Our members meet at Hacker Dojo in Mountain View and online. We also organized seminars and hackathons abroad in Mexico, Armenia, Azerbaijan, Georgia, Kyrgyzstan and other places.

Videos from our recent hackathon in Armenia: