Some highlights from the Verilog Meetup workshop we did at Universidad autónoma de Baja California in Tijuana last week: The participating students were familiar with the logic gates and flip-flops but had no prior experience with the hardware description languages. After 1 1/2 days they were able to code combinational […]

Instructions for Verilog Meetup examples are now available in 5 languages: English, Spanish, Russian, Ukrainian and Belarusian. English GOWIN EDA Quick Start Guide V6 TangNano9KBoardSetupV3 Tang Nano 9K Synthesis and Configuration V6 Spanish GOWIN EDA Quick Start Guide Spanish V1 Tang Nano 9K Board Setup Spanish V1 Tang Nano 9K […]

The industry needs interns trained in pipelined microarchitecture and timing, with solid coding skills Every year, electronic companies get new interns from the universities. Some interns become very useful, contributing pieces of design that eventually become silicon inside mass-market commercial devices. To accomplish this, an RTL or DV intern should […]

Flow control is a crucial synchronization technique for data transmission. It ensures the efficient flow of data between the transmitter and receiver by maintaining a balance between the data production rate of the sender and the data consumption rate of the receiver. The data that is being transmitted is buffered […]

The dates for the Verilog Meetup events in Mexico and Armenia are set: Friday and Saturday, February 21-22, 2025 in Mexico, Universidad autónoma de baja California in Tijuana. Thursday and Friday, March 13-14, 2025 in Armenia, Russian-Armenian University in Yerevan, in cooperation with the Institute for Informatics and Automation Problems, […]

The State of Caravel: the First Look Yuri Panchul, 2025.01.22 This text is a mix of my thoughts on using Caravel and Open Lane together with a report on my first attempt to do the following: Setup on 5 platforms: three Linux distributions, Windows and MacOS. Running RTL-to-GDSII flow for […]