Thank you for attending the Verilog Meetup booth at Maker Faire. We decided to write a brief follow-up letter for all our attendees before following up individually, and put all the links into this post.

For high school students interested in exploring how chips are designed: you can attend our weekly meetups in Mountain View or a planned session in San Francisco. We will bring a dozen FPGA boards with LCD screens and you can create graphical games by manipulating code in SystemVerilog hardware description language.

For high school teachers living in the San Francisco Bay Area: we can schedule a meeting with you in your school and walk with you through our examples. Then you can decide whether you want us to make a session with students in your school or integrate this technology into your curriculum.

A tentative plan for a session is described in a post Between Physics and Programming: a Workshop on a Hardware Description Language SystemVerilog used to design silicon chips.

For educators living not within driving distance, we can hold such meetings over Zoom. Just contact Yuri Panchul at yuri@panchul.com or via LinkedIn.

For university or college students who study Digital Design and Computer Architecture: you can check our GitHub repositories: one is systemverilog-homework, which helps to train in SystemVerilog – from zero to job-interview level microarchitecture questions on pipelining and data flow control. Another is basics-graphics-music, which contains examples that run on 40 different FPGA boards using 5 toolchains. We would also appreciate it if you could check whether your professor is interested in Verilog Meetup making a presentation at your school.

For professionals in other fields, from machine learning to biology, who are interested in learning the basics of register-transfer level design to use FPGAs in, for example, lab equipment, you can check our post that contains recommendations on how to get the necessary skills to process a stream of data: Self-education and educating others.

For those who want to do joint hardware projects, create instructional materials, or organize a session in their hacker space, please contact Yuri Panchul at yuri@panchul.com or via LinkedIn.

In addition to this workshop proposal, we are working on a hackathon proposal in which the participants prototype graphical games on Gowin FPGA boards, present them to a panel of judges and gamers, and finally implement the games in ASIC using TinyTapeout and eFabless. The games will be primarily judged on how cool they are; however they must pass all the technical criteria, including the absence of verilator lint warnings and no negative slack in static timing analysis for both FPGA and ASIC implementation. We also intend to restrict the games in size (like up to 4 TinyTapeout tiles) and prohibit the use of CPU cores in the design (otherwise, the competition will be dominated by retrocomputing fans bringing back to life their favorite games from the 1980s). The focus of the competition should be on how much fun you can get from clever hardware design rather than from software (which already has a lot of competitions).

A tentative hackathon set:

An example of a game:

A demo at eFabless both at Maker Faire:

A summary of hardware vs software:

Thank you from the Verilog Mettup team at Maker Faire: