My name is Philip Sisa M, having worked in telecommunication industry for more than 8 years as a cellular Radio Access Network integration contractor, I decided to make a career change to Register Transfer Language ( RTL ) design related role. I have Electrical and Electronic Engineering background. To expedite this transition I did an online FPGA Design specialization and joined Verilog meetup group after contacting Yuri Panchul from Samsung on Linkedin. This group has RTL homework assignments that checks or improvements quality of a member, I am working on micro-architectural part of this, which I hope to finish soon.
Why RTL design, RTL design leads to a physical realization of a chip if the toolchain of interest is to produce an Application Specific Integrated Circuite ( ASIC ). Also, the logic can be mapped to an Field Programmable Gate Array ( FPGA ) to be deployed in systems for instance telecommunication, defense and space. This is a valuable skill, one could leverage this to implement portable Intellectual Properties ( IP ) to be licensed at a cost. There are other methods of design synthesis-able logic, namely, use of AI, use of chisel-lang (which is based on Scala library that generates Verilog code) and High Level Synthesis (use of C++ or C to produce Verilog file) this alternatives have not been adopted by front-end logic design semiconductor industry. The year 2024, Systemverilog seem to be taking a lead in India and USA chip design companies. This is attributed to its rich features as well as verification preference in this industry.
Contribution of RTL designs systems in telecom industry is immense. Signal processing part of this systems that involves fixed point math operations are efficiently implemented using FPGAs, this makes it possible for vendors like Nokia, Ericsson and Huawei to implement a cellular network like Safaricom in Kenya. As a mobile provider Safaricom has transformed peoples lives in various ways, Government services for instance, passport applications is done online leveraging this widely distributed network across the country. Also, Mobile money service M-Pesa launched by this provider handles more than 10 million transaction daily, contributing hugely to Kenyan economy.
My near future contribution. After finishing micro-architectural assignment I would like to take a project, habr.com 51 of this group CPU: Connect a cache from the appendix Patterson-Hennessy textbook (5th Edition) to the MIRISC core and demonstrate the performance changes with different memory access patterns.
MIRISCV pipelined core:
A excerpts from Patterson-Hennessy materials:
